Closer Look: Core i5-2500K

The launch of Sandy Bridge brings a whole new architecture to the table. This was also the case when Clarkdale/Arrandale launched and we moved to the LGA1156 socket. With those processors, the 32nm CPU and 45nm GPU were combined onto the same die. This was the first large-scale release of on-die graphics, though they had been talked about for a long time. In the Sandy Bridge architecture, the on-die GPU moves to a 32nm process as well and the IMC moves onto the die. The smaller process lets Intel use roughly the same amount of space for the new Sandy Bridge die, but it can fit a lot more transistors.

Another difference is that Sandy Bridge CPUs will come with one of two versions of the on-die graphics; either the 2000 or the 3000 version. Also, while Clarkdale/Arrandale processors took advantage of turbo boost, Sandy Bridge boasts turbo boost usage for the GPU independent of the CPU. This is good news for gamers who choose to use the on-die graphics. If their game, like most, requires heavy GPU loads, the turbo boost can leave the CPU at stock speeds and clock up the GPU to improve performance.

The Intel Core i5-2500K comes equipped with a 6MB shared L3 cache. Since the Nehalem architecture, where each core had a dedicated 2MB of cache, Intel has gone towards shared cache. In the Sandy Bridge architecture, the L3 cache is not only shared across all four cores of the Core i5-2500K, but also with the integrated GPU.

Another interesting cache feature of the Sandy Bridge CPUs is a tiny L0 instruction cache integrated with the L1 cache known as a Decoded Uop Cache. This caches instructions as they are decoded without discrimination. All decoded instructions run through this ~6KB cache. Old instructions are overwritten as new ones come along. This cache is designed to help alleviate front-end operation for commonly performed tasks.

Intel has also added a physical register file to their Sandy Bridge CPUs. AMD has talked about doing the same thing and it's a product of the growing size of Out-Of-Order execution hardware. It's grown quite a bit and with the inclusion of Advanced Vector Extensions (AVX) in the Sandy Bridge, the size of operands running through the OoO hardware would have become 256-bits. So Intel decided to put in a physical register file that will store the micro-op operands allowing the OoO to only carry pointers, rather than the data itself. Additionally, Sandy Bridge keeps the AES-NI introduced in Westmere and enhances Large Number Arithmetic Throughput. We should notice this in our CPU tests, especially the arithmetic processor tests and compression tests.

In order to speed up processing, Intel changed the way the parts of the die interconnect by creating what they call a ring bus. Older Intel architecture had each core with a separate path to the L3 cache. This isn't so bad if every core has its own cache, but when you have a shared cache between all the cores and the GPU, there isn't a lot of room to give everything its own path. The ring bus works basically how it sounds and each component of the die has its own location along the bus. Doing things this way gives the Sandy Bridge L3 cache great bandwidth and helps to reduce latency.

With everything on die now, we are moving away from older terminology like "Northbridge". The Sandy Bridge CPUs have a "System Agent" that controls the 16 PCI Express Lanes (they can be split into two x8 lanes), the DMI interface, the Memory Controller, and the Display Engine. The system agent also has a power control unit that controls all power management and reset functions, has separate voltage and frequency than the CPU cores, and offers power and thermal management for the PCI Express.

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