Nehalem Architecture

With more powerful processors, a potential bottleneck can form anytime a processor or its individual cores can't fetch instructions and data as fast as they're being executed. Whenever this happens, performance slows. Of particular importance to the performance of a system is the speed at which a microprocessor and its execution cores can access system memory (in addition to internal cache). In multi-processor systems, not only is the actual access to data important, but also the multi-processor communication required to ensure memory coherency (also called snoop traffic).

For years Intel kept instructions and data flowing quickly to the processor through an external bi-directional data bus called a front-side bus (FSB). This bus performed as a backbone between the processor cores and a chipset that contained the memory controller hub and served as the connection point for all other buses (PCI, AGP, etc.) in the system. In turn, this has delivered industry-leading processor performance on the Intel Core micro architecture family of processors.

In its long-range planning, Intel has long anticipated that the development of a high-performance, dynamically, and design-scalable micro architecture like next generation Intel micro architecture (Nehalem) would lead to moving beyond FSBs to a new system architecture. The result was the development of Intel QuickPath Architecture, a new system architecture that integrates a memory controller into each microprocessor, dedicates specific areas of system memory to each processor, and connects processors and other components with a new high-speed interconnect. Previously referenced under the code name Common System Interface or CSI, Intel QuickPath Interconnect unleashes the performance of next generation micro architecture-based processors and future generations of Intel multi-core processors.

Intel QuickPath Architecture is a platform architecture that provides high-speed connections between microprocessors and external memory, and between microprocessors and the I/O hub. One of its biggest changes is the implementation of scalable shared memory. Instead of using a single shared pool of memory connected to all the processors in a server or high-end workstation through FSBs and memory controller hubs, each processor has its own dedicated memory that it accesses directly through an Integrated Memory Controller on the processor die. (For dual-core desktop and mobile processors, the memory controller will be implemented in the processor package.) In cases where a processor needs to access the dedicated memory of another processor, it can do so through a high-speed Intel QuickPath Interconnect that links all the processors.

An advantage of Intel QuickPath Interconnect is that it is point-to-point. There is no single bus that all the processors must use and contend with each other to reach memory and I/O. This improves scalability and eliminates the competition between processors for bus bandwidth.

Features & Specifications

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